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HIGH-SPEED 64K x 16 BANK-SWITCHABLE DUAL-PORTED SRAM WITH EXTERNAL BANK SELECTS
x
IDT707288S/L
Features
64K x 16 Bank-Switchable Dual-Ported SRAM Architecture - Four independent 16K x 16 banks - 1 Megabit of memory on chip Fast asynchronous address-to-data access time: 15ns User-controlled input pins included for bank selects Independent port controls with asynchronous address & data busses Four 16-bit mailboxes available to each port for interx x
x x x
x x x
processor communications; interrupt option Interrupt flags with programmable masking Dual Chip Enables allow for depth expansion without external logic UB and LB are available for x8 or x16 bus matching TTL-compatible, single 5V (10%) power supply Available in a 100-pin Thin Quad Flatpack (14mm x 14mm)
x
Functional Block Diagram
MUX R/WL CE0L CE1L UBL LBL OEL 16Kx16 MEMORY ARRAY (BANK 0) MUX I/O8L-15L I/O0L-7L I/O CONTROL MUX 16Kx16 MEMORY ARRAY (BANK 1) MUX I/O CONTROL I/O8R-15R I/O0R-7R R/WR CE0R CE1R UBR LBR OER
CONTROL LOGIC
CONTROL LOGIC
A13L A0L(1)
ADDRESS DECODE
ADDRESS DECODE
A13R A0R(1)
BA1L BA0L
BANK DECODE MUX 16Kx16 MEMORY ARRAY (BANK 3) MUX
BANK DECODE
BA1R BA0R
BKSEL3(2) BKSEL0(2)
BANK SELECT A5L(1) A0L(1) LBL/UBL OEL R/WL CEL MAILBOX INTERRUPT LOGIC A5R(1) A0R(1) LBR/UBR OER R/WR CER
MBSELL INTL
MBSELR INTR
3592 drw 01
NOTES: 1. The first six address pins for each port serve dual functions. When MBSEL = VIH, the pins serve as memory address inputs. When MBSEL = VIL, the pins serve as mailbox address inputs. 2 . Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Truth Table I for more details.
MAY 2000
1
(c)2000 Integrated Device Technology, Inc. DSC 3592/7
IDT707288S/L High-Speed 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT707288 is a high-speed 64K x 16 (1M bit) Bank-Switchable Dual-Ported SRAM organized into four independent 16K x 16 banks. The device has two independent ports with separate control, address, and I/O pins for each port, allowing each port to asynchronously access any 16K x 16 memory block not already accessed by the other port. Accesses by the ports into specific banks are controlled via bank select pin inputs under the user's control. Mailboxes are provided to allow interprocessor communication. Interrupts are provided to indicate mailbox writes have occurred. An automatic power down feature controlled by the chip enables (CE0 and CE1) permits the on-chip circuitry of each port to enter a very low standby power mode and allows fast depth expansion. The IDT707288 offers a maximum address-to-data access time as fast as 15ns, and is packaged in a 100-pin Thin Quad Flatpack (TQFP). IV). Once a bank is assigned to a particular port, the port has full access to read and write within that bank. Each port can be assigned as many banks within the array as needed, up to and including all four banks. The IDT707288 provides mailboxes to allow inter-processor communication. Each port has four 16-bit mailbox registers available to which it can write and read and which the opposite port can read only. These mailboxes are external to the common SRAM array, and are accessed by setting MBSEL = VIL while setting CE = VIH. Each mailbox has an associated interrupt: a port can generate an interrupt to the opposite port by writing to the upper byte of any one of its four 16-bit mailboxes. The interrupted port can clear the interrupt by reading the upper byte. This read will not alter the contents of the mailbox. If desired, any source of interrupt can be independently masked via software. Two registers are provided to permit interpretation of interrupts: the Interrupt Cause Register and the Interrupt Status Register. The Interrupt Cause Register gives the user a snapshot of what has caused the interrupt to be generated - the specific mailbox written to. The information in this register provides post-mask signals: interrupt sources that have been masked will not be updated. The Interrupt Status Register gives the user the status of all bits that could potentially cause an interrupt regardless of whether they have been masked. Truth Table V gives a detailed explanation of the use of these registers.
Functionality
The IDT707288 is a high-speed asynchronous 64K x 16 BankSwitchable Dual-Ported SRAM, organized in four 16K x 16 banks. The two ports are permitted independent, simultaneous access into separate banks within the shared array. There are four user-controlled Bank Select input pins, and each of these pins is associated with a specific bank within the memory array. Access to a specific bank is gained by placing the associated Bank Select pin in the appropriate state: VIH assigns the bank to the left port, and VIL assigns the bank to the right port (See Truth Table
6.42 2
IDT707288S/L High-Speed 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
INDEX
A6L A7L A8L A9L A10L A11L A13L NC BKSEL0 LBL UBL CE0L CE1L MBSELL Vcc R/WL OEL GND GND I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L
1 2 3 4 5 6 7 8 9
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
A5L A4L A3L A2L A1L A0L BA1L BA0L A12L NC BKSEL1 INTL GND GND INTR BKSEL2 A12R BA0R BA1R A0R A1R A2R A3R A4R A5R
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Pin Configurations
(1,2,3)
IDT707288PF PN100-1(4) 100-Pin TQFP Top View(5)
51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A6R A7R A8R A9R A10R A11R A13R NC BKSEL3 LBR UBR CE0R CE1R MBSELR GND R/WR OER GND GND I/O15R I/O14R I/O13R I/O12R I/O11R I/O10R
3592 drw 02
NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground supply. 3. Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.
I/O9L I/O8L Vcc I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R Vcc I/O7R I/O8R I/O9R NC
,
Pin Names
A0 - A13(1,6) BA0 - BA1(1) MBSEL(1) BKSEL0-3 R/W OE
(1) (2)
Address Inputs Bank Address Inputs Mailbox Access Control Gate Bank Select Inputs Read/Write Enable Output Enable Chip Enables I/O Byte Enables
(1)
CE0, CE1(1) UB, LB
(1) (1)
I/O0 - I/O15 INT
(1)
Bidirectional Data Input/Output Interrupt Flag (Output)(3) +5VPower Ground
3592 tbl 01
VCC(4) GND
(5)
NOTES: 1. Duplicated per port. 2. Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Truth Table IV for more details. When changing the bank assignments, accesses of the affected banks must be suspended. Accesses may continue uninterrupted in banks that are not being reallocted. 3. Generated upon mailbox access. 4. All Vcc pins must be connected to power supply. 5. All GND pins must be connected to ground supply. 6. The first six address pins (A0-A5) for each port serve dual functions. When MBSEL = VIH, the pins serve as memory address inputs. When MBSEL = VIL, the pins serve as mailbox address inputs (A6-A13 are ignored).
3 6.42
IDT707288S/L High-Speed 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I Chip
CE CE0 VIL L < 0.2V VIH H X >VCC -0.2V X
Enable(1,2,3,4)
CE1 VIH >VCC -0.2V X VIL X <0.2V Port Selected (TTL Active) Port Selected (CMOS Active) Port Deselected (TTL Inactive) Port Deselected (TTL Inactive) Port Deselected (CMOS Inactive) Port Deselected (CMOS Inactive)
3592 tbl 02
Mode
NOTES: 1. Chip Enable references are shown above with the actual CE0 and CE1 levels; CE is a reference only. 2. Port "A" and "B" references are located where CE is used. 3. "H" = VIH and "L" = VIL. 4. CE and MBSEL cannot both be active at the same time.
Truth Table II Non-Contention Read/Write Control
Inputs(1) CE(2) H X(3) L L L L L L X
(3)
Outputs UB X H L H L L H L X LB X H H L L H L L X MBSEL H X(3) H H H H H H X
(3)
R/W X X L L L H H H X
OE X X X X X L L L H
I/O8-15 High-Z High-Z DATAIN High-Z DATAIN DATAOUT High-Z DATAOUT High-Z
I/O0-7 High-Z High-Z High-Z DATAIN DATAIN High-Z DATAOUT DATAOUT High-Z Deselcted: Power-Down Both Bytes Deselected
Mode
Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Read Upper Byte Only Read Lower Byte Only Read Both Bytes Outputs Disabled
3592 tbl 03
NOTES: 1. BA0L - BA1L BA0R - BA1R: cannot access same bank simultaneously from both ports. 2. Refer to Truth Table I. 3. CE and MBSEL cannot both be active at the same time.
Truth Table III Mailbox Read/Write Control(1)
Inputs CE(2) H H H L R/W H H L X OE L L X X UB X L L(3) X
(3)
Outputs LB X L L(3) X
(3)
MBSEL L L L L
I/O8-15 DATAOUT DATAOUT DATAIN
____
I/O0-7 DATAOUT DATAOUT DATAIN
____
Mode Read Data from Mailbox, clears interrupt Read Data from Mailbox, clears interrupt Write Data into Mailbox Not Allowed
3592 tbl 04
NOTES: 1. There are four mailbox locations per port written to and read from all the I/O's (I/O0-I/O15). These four mailboxes are addressed by A0-A5. Refer to Truth Table V. 2. Refer to Truth Table I. 3. Each mailbox location contains a 16-bit word, controllable in bytes by setting input levels to UB and LB appropriately.
6.42 4
IDT707288S/L High-Speed 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature DC Output Current Commercial & Industrial -0.5 to +7.0 Unit V
Maximum Operating Temperature and Supply Voltage(1)
Grade Commercial Ambient Temperature 0OC to +70OC -40OC to +85OC GND 0V 0V Vcc 5.0V + 10% 5.0V + 10%
3592 tbl 06
TBIAS TSTG IOUT
-55 to +125 -65 to +150 50
o
C C
Industrial
o
NOTES: 1. This is the parameter TA. This is the "instant on" case temperature.
mA
3592 tbl 05
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
Recommended DC Operating Conditions
Symbol VCC GND VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5(1) Typ. 5.0 0
____
Max. 5.5 0 6.0
(2)
Unit V V V V
3592 tbl 07
____
0.8
Capacitance(1)
Symbol CIN COUT
(3)
(TA = +25C, f = 1.0mhz) TQFP Package
Parameter Input Capacitance Output Capacitance Conditions(2) VIN = 3dV VOUT = 3dV Max. 9 10 Unit pF pF
3592 tbl 08
NOTES: 1. VIL > -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%.
NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV represents the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V. 3. COUT represents CI/O as well.
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VCC = 5.0V 10%)
707288S Symbol |ILI| |ILO| VOL VOH Parameter Input Leakage Current(1) Output Leakage Current Output Low Voltage Output High Voltage Test Conditions VCC = 5.5V, VIN = 0V to VCC CE = VIH, MBSEL = VIH, VOUT = 0V to VCC IOL = +4mA IOH = -4mA Min.
___
707288L Min.
___
Max. 10 10 0.4
___
Max. 5 5 0.4
___
Unit A A V V
3592 tbl 09
___
___
___
___
2.4
2.4
NOTE: 1. At Vcc < 2.0V, input leakages are undefined.
5 6.42
IDT707288S/L High-Speed 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1,6) (VCC = 5.0V 10%)
707288X15 Com'l Only Symbol ICC Parameter Dynamic Operating Current (Both Ports Active) Test Condition CE = VIL, Outputs Disabled MBSEL = VIH f = fMAX(3) Version COM'L IND COM'L IND COM'L IND COM'L IND COM'L IND S L S L S L S L S L S L S L S L S L S L Typ.(2) 220 220
____ ____
707288X20 Com'l & Ind Typ.(2) 200 200 250 250 45 45 45 45 120 120 140 140 1.5 1.5 1.5 1.5 135 135 135 135 Max. 340 290 370 320 90 65 100 75 215 185 235 205 15 5 30 10 210 180 230 200
707288X25 Com'l & Ind Typ.(2) 190 190 240 240 40 40 40 40 110 110 130 130 1.5 1.5 1.5 1.5 130 130 130 130 Max. 330 280 360 310 90 65 100 75 200 170 220 190 15 5 30 10 200 170 220 190
3592 tbl 10
Max. 350 300
____ ____
Unit mA
ISB1
Standby Current (Both Ports - TTL Level Inputs)
CEL = CER = VIH MBSELR = MBSELL = VIH f = fMAX(3)
50 50
____ ____
90 65
____ ____
mA
ISB2
Standby Current (One Port - TTL Level Inputs)
CE"A" = VIL and CE"B" = VIH(5) Active Port Outputs Disabled, f=fMAX(3) MBSELR = MBSELL = VIH Both Ports CEL and CER > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0(4) MBSELR = MBSELL > VCC - 0.2V CE"A" < 0.2V and CE"B" > VCC - 0.2V(5) MBSELR = MBSELL > VCC - 0.2V VIN > VCC - 0.2V or VIN < 0.2V Active Port Outputs Disabled f = fMAX(3)
130 130
____ ____
230 200
____ ____
mA
ISB3
Full Standby Current (Both Ports - All CMOS Level Inputs)
1.5 1.5
____ ____
15 5
____ ____
mA
ISB4
Full Standby Current (One Port - All CMOS Level Inputs)
145 145
____ ____
230 195
____ ____
mA
NOTES: 1. 'X' in part numbers indicates power rating (S or L). 2. VCC = 5V, TA = +25C, and are not production tested. ICCDC = 120mA (Typ.) 3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using "AC Test Conditions" of input levels of GND to 3V. 4. f = 0 means no address or control lines change. 5. Port "A" may be either left or right port. Port "B" is the opposite from port "A". 6. Refer to Truth Table I.
6.42 6
IDT707288S/L High-Speed 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
5V 5V 893 DATAOUT INT 347 30pF DATAOUT 347 5pF* 893
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 3ns Max. 1.5V 1.5V Figures 1,2 and 3
3592 tbl 11
3592 drw 04
8 7 6 AEtACE/tAA
(Typical, ns)
- 10pF is the I/O capacitance of this device, and 30pF is the AC Test Load Capacitance
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW) *Including scope and jig.
5 4 3 2 1 0 -1 20 40 60 80 100 120 140 160 180 200 Capacitance (pF)
3592 drw 05 ,
Figure 3. Lumped Capacitance Load Typical Derating Curve
AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(4)
707288X15 Com'l Only Symbol READ CYCLE tRC tAA tACE tABE tAOE tOH tLZ tHZ tPU tPD tMOP tMAA Read Cycle Time Address Access Time Chip Enable Access Time (3) Byte Enable Access Time (3) Output Enable Access Time Output Hold from Address Change Output Low-Z Time
(1,2) (1,2) (2,5) (2,5)
707288X20 Com'l & Ind Min. Max.
707288X25 Com'l & Ind Min. Max. Unit
Parameter
Min.
Max.
15
____
____
20
____
____
25
____
____
ns ns ns ns ns ns ns ns ns ns ns ns
3592 tbl 12
15 15 15 9
____
20 20 20 10
____
25 25 25 11
____
____
____
____
____
____
____
____
____
____
3 0
____
3 0
____
3 0
____
____
____
____
Output High-Z Time
8
____
9
____
10
____
Chip Enable to Power Up Time
0
____
0
____
0
____
Chip Disable to Power Down Time
15
____
20
____
25
____
Mailbox Flag Update Pulse (OE or MBSEL) Mailbox Address Access Time
10
____
10
____
10
____
15
20
25
NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL and MBSEL = VIH. To access mailbox, CE = VIH and MBSEL = VIL. 4. 'X' in part numbers indicates power rating (S or L). 5. Refer to Truth Table I.
7 6.42
IDT707288S/L High-Speed 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Assigning the Banks via the External Bank Selects
There are four bank select pins available on the IDT707288, and each of these pins is associated with a specific bank within the memory array. The pins are user-controlled inputs: access to a specific bank is assigned to a particular port by setting the input to the appropriate level. The process of assigning the banks is detailed in Truth Table IV. Once a bank is assigned to a port, the owning port has full access to read and write within that bank. The opposite port is unable to access that bank until the user reassigns the port. Access by a port to a bank which it does not control will have no effect if written, and if read unknown values on D0-D15 will be returned. Each port can be assigned as many banks within the array as needed, up to and including all four banks. The bank select pin inputs must be set at either VIH or VIL - these inputs are not tri-statable. When changing the bankassignments, accesses of the affected banks must be suspended. Accesses may continue uninterrupted in banks that are not being reallocated.
Truth Table IV Memory Bank Assignment (CE = VIH)(2,3)
BKSEL0 H X X X L X X X BKSEL1 X H X X X L X X BKSEL2 X X H X X X L X BKSEL3 X X X H X X X L BANK AND DIRECTION(1) BANK 0 LEFT BANK 1 LEFT BANK 2 LEFT BANK 3 LEFT BANK 0 RIGHT BANK 1 RIGHT BANK 2 RIGHT BANK 3 RIGHT
3592 tbl 13 NOTES: 1 . Bank 0 refers to the first 16Kx16 memory spaces, Bank 1 to the second 16Kx16 memory spaces, Bank 2 to the third 16Kx16 memory spaces, and Bank 3 to the fourth 16Kx16 memory spaces. 'LEFT' indicates the bank is assigned to the left port; 'RIGHT' indicates the bank is assigned to the right port. 0-4 banks may be assigned to either port. 2 . The bank select pin inputs must be set at either VIH or VIL - these inputs are not tri-statable. When changing the bank assignments, accesses of the affected banks must be suspended. Accesses may continue uninterrupted in banks that are not beign reallocated. 3 . 'H' = VIH, 'L' = VIL, 'X' = Don't Care.
Mailbox Interrupts and Interrupt Control Registers
If the user chooses the mailbox interrupt function, four mailbox locations are assigned to each port. These mailbox locations are external to the memory array. The mailboxes are accessed by setting MBSEL = VIL while holding CE = VIH. The mailboxes are 16 bits wide and controllable by byte: the message is user-defined since these are addressable SRAM locations. An interrupt is generated to the opposite port upon writing to the upper byte of any mailbox location. A port can read the message it has just written in order to verify it: this read will not alter the status of the interrupt sent to the opposite port. The interrupted port can clear the interrupt by reading the upper byte of the applicable mailbox. This read will not alter the contents of the mailbox. The use of mailboxes to generate interrupts to the opposite port and the reading of mailboxes to clear interrupts is detailed in Truth Table V. If desired, any of the mailbox interrupts can be independently masked via software. Masking of the interrupt sources is done in the Mask Register. The masks are individual and independent: a port can mask any combination of interrupt sources with no effect on the other sources. Each port can modify only its own Mask Register. The use of this register is detailed in Truth Table V. Two registers are provided to permit interpretation of interrupts: these are the Interrupt Cause Register and the Interrupt Status Register. The Interrupt Cause Register gives the user a snapshot of what has caused the interrupt to be generated - the specific mailbox written to by the opposite port. The information in this register provides post-mask signals: interrupt sources that have been masked will not be updated. The Interrupt Status Register gives the user the status of all bits that could potentially cause an interrupt regardless of whether they have been masked. The use of the Interrupt Cause Register and the Interrupt Status Register is detailed in Truth Table V.
6.42 8
IDT707288S/L High-Speed 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table V Mailbox Interrupts (CE = VIH)(8,9)
MB SEL L L L L L L L L L R/W X X (1) (1) (1) (1) H H H H (3) X X UB X X (1) (1) (1) (1) (2) (2) (2) (2) (3) X X LB X X (1) (1) (1) (1) (2) (2) (2) (2) (3) X X A5 L
* * *
A4 L
* * *
A3 L
* * *
A2 L
* * *
A1 L
* * *
A0 L
* * *
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
DESCRIPTION RESERVED (7) RESERVED (7)
RESERVED (7) RESERVED (7) X X X X X X X X (4) X X X X X X X X (4) X X X X X X X X (4) X X X X X X X X (4) X X X X X X X X (5) X X X X X X X X (5) X X X X X X X X (5) X X X X X X X X (5) X X X X X X X X (6) X X X X X X X X (6) X X X X X X X X (6) X X X X X X X X (6) X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X
H H H H H H H H H
* * *
L L L L L L L L L
* * *
L L L L L L L L H
* * *
L L L L H H H H L
* * *
L L H H L L H H L
* * *
L H L H L H L H L
* * *
MAILBOX 0 - SET INTERRUPT ON OPPOSITE PORT MAILBOX 1 - SET INTERRUPT ON OPPOSITE PORT MAILBOX 2 - SET INTERRUPT ON OPPOSITE PORT MAILBOX 3 - SET INTERRUPT ON OPPOSITE PORT MAILBOX 0 - CLEAR OPPOSITE PORT INTERRUPT MAILBOX 1 - CLEAR OPPOSITE PORT INTERRUPT MAILBOX 2 - CLEAR OPPOSITE PORT INTERRUPT MAILBOX 3 - CLEAR OPPOSITE PORT INTERRUPT MAILBOX INTERRUPT CONTROLS RESERVED (7) RESERVED (7)
3592 tbl 14
RESERVED (7) RESERVED (7)
H
H
H
H
H
H
NOTES: 1. There are four independent mailbox locations available to each side, external to the standard memory array. The mailboxes can be written to in either 8-bit or 16-bit widths. The upper byte of each mailbox has an associated interrupt to the opposite port. The mailbox interrupts can be individually masked if desired, and the status of the interrupt determined by polling the Interrupt Status Register (see Note 6 for this table). A port can read its own mailboxes to verify the data written, without affecting the interrupt which is sent to the opposite port. 2. These registers allow a port to read the data written to a specific mailbox location by the opposite port. Reading the upper byte of the data in a particular mailbox clears the interrupt associated with that mailbox without modifying the data written. Once the address and R/W are stable, the actual clearing of the interrupt is triggered by the transition of MBSEL from VIH to VIL. 3. This register contains the Mask Register (bits D0-D3), the Interrupt Cause Register (bits D4-D7), and the Interrupt Status Register (bits D8-D11). The controls for R/W, UB, and LB are manipulated in accordance with the appropriate function. See Notes 4, 5, and 6 for this table. Bits D12-D15 are "Don't Care". 4. This register, the Mask Register, allows the user to independently mask the various interrupt sources. Writing VIH to the appropriate bit (D0 = Mailbox 0, D1 = Mailbox 1, D2 = Mailbox 2, and D3 = Mailbox 3) disables the interrupt, while writing VIL enables the interrupt. All four bits in this register must be written at the same time. This register can be read at any time to verify the mask settings. The masks are individual and independent: any single interrupt source can be masked with no effect on the other sources. Each port can modify only its own mask settings. 5. This register, the Interrupt Cause Register, gives the user a snapshot of what has caused the interrupt to be generated. Reading VOL for a specific bit (D4 = Mailbox 0, D5 = Mailbox 1, D6 = Mailbox 2, and D7 = Mailbox 3) indicates that the associated interrupt source has generated an interrupt. Acknowledging the interrupt clears the bit in this register (see Note 2 for this table). This register provides post-mask information: if the interrupt source has been masked, the associated bit in this register will not update. 6. This register, the Interrupt Status Register, gives the user the status of all interrupt sources that could potentially cause an interrupt regardless of whether they have been masked. Reading VOL for a specific bit (D8 = Mailbox 0, D9 = Mailbox 1, D10 = Mailbox 2, and D11 = Mailbox 3) indicates that the associated interrupt source has generated an interrupt. Acknowledging the interrupt clears the associated bit in this register (see Note 2 for this table). This register provides pre-mask information: regardless of whether an interrupt source has been masked, the associated bit in this register will update. 7. Access to registers defined as "RESERVED" will have no effect, if written, and if read unknown values on D0-D15 will be returned. 8. These registers are not guaranteed to initialize in any known state. At power-up, the initialization sequence should include the set-up of these registers. 9. 'L' = VIL or VOL, 'H' = VIH or VOH, 'X' = Don't Care.
9 6.42
IDT707288S/L High-Speed 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Read Cycles
ADDR
(4)
tRC
CE
(5)
tAA (3) tACE tAOE
(3)
(3)
OE
tABE UB, LB
(3)
R/W tLZ DATAOUT
(1)
tOH VALID DATA
(3) (2) 3592 drw 06
tHZ
NOTES: 1. Timing depends on which signal is asserted last, CE, OE, LB, or UB. 2. Timing depends on which signal is de-asserted first CE, OE, LB, or UB. 3. Start of valid data depends on which timing becomes effective last: tAOE, tACE, tABE or tAA. 4. MBSEL = VIH. 5. Refer to Truth Table I.
Timing of Power-Up Power-Down
CE ICC ISB
3592 drw 07
(5)
tPU
50%
tPD
50%
,
6.42 10
IDT707288S/L High-Speed 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature and Supply Voltage(5)
707288X15 Com'l Only Symbol WRITE CYCLE tWC tEW tAW tAS tBS tWP tWR tDW tHZ tDH tWZ tOW tMWRD Write Cycle Time Chip Enable to End-of-Write
(3)
707288X20 Com'l & Ind Min. Max.
707288X25 Com'l & Ind Min. Max. Unit
Parameter
Min.
Max.
15 12 12 0 0 12 0 15
____
____
20 15 15 0 0 15 0 15
____
____
25 20 20 0 0 20 0 20
____
____
ns ns ns ns ns ns ns ns ns ns ns ns ns
3592 tbl 15
____
____
____
Address Valid to End-of-Write Address Set-up Time (3) Bank Set-up Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Output High-Z Time Data Hold Time(4) Write Enable to Output in High-Z Output Active from End-of-Write Mailbox Write to Read Time
(1,2) (1,2)
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
8
____
9
____
10
____
0
____
0
____
0
____
8
____
9
____
10
____
(1,2,4)
3 5
3 5
3 5
____
____
____
NOTES: 1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). 2. This parameter is guaranteed by device characterization, but is not production tested. 3. To access RAM, CE = VIL and MBSEL = VIH. To access mailbox, CE = VIH and MBSEL = VIL. Either condition must be valid for the entire tEW time. Refer to Truth Tables I and III. 4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. 5. 'X' in part numbers indicates power rating (S or L).
11 6.42
IDT707288S/L High-Speed 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC ADDRESS tHZ OE tAW CE or MBSEL UB or LB
(9) (9,10) (7)
tAS (6) R/W tLZ DATAOUT tWZ (7) VALID
(4)
tWP
(2)
tWR
(3)
tOW
(4)
tDW DATAIN
tDH
3592 drw 08
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)
tWC ADDRESS tAW CE or MBSEL
(9,10) (6) (3)
tAS UB or LB
(9)
tEW (2)
tWR
R/W tDW DATAIN
3592 drw 09
tDH
NOTES: 1. R/W or CE or UB and LB = VIH during all address transitions. 2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL for memory array writing cycle. 3. tWR is measured from the earlier of CE or R/W (or MBSEL or R/W) going to VIH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CE or MBSEL = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state. 6. Timing depends on which enable signal is asserted last, CE or R/W. 7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure 2). 8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9. To access RAM, CE = VIL and MBSEL = VIH. To access mailboxes, CE = VIH and MBSEL = VIL. tEW must be met for either condition. 10. Refer to Truth Table I.
6.42 12
IDT707288S/L High-Speed 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Left Port Write to right Port Read of Same Data(1,2,3)
tWC A0L-13L and A0R-13R tAW CEL tEW tWR ADDRESSES MATCH
CER tBS BKSEL0-3 tAS R/WL tDW I/O0L-15L tDH tWP
tACE
DATAIN VALID
R/WR
OER tOH I/O0R-15R
Write Cycle
tLZ
Read Cycle
DATAOUT VALID tHZ
3592 drw 10
,
NOTES: 1. UB and LB are controlled as necessary to enable the desired byte accesses. 2. Timing for Right Port Write to Left Port Read is identical. 3. Refer to Truth Table I and IV.
Timing Waveform of Mailbox Read after Write Timing, Either Side(1,2)
tMAA A0-A5 VALID ADDRESS tAW MBSEL tDW DATAIN VALID tAS R/W tMWRD OE
Write Cycle Read Cycle
3592 drw 11
tOH
VALID ADDRESS tACE tMOP DATAOUT VALID
tWR tEW
I/O0-15 tWP
tDH
tAOE
NOTES: 1. CE = VIH for the duration of the above timing (both write and read cycle), refer to Truth Table I. 2. UB and LB are controlled as necessary to enable the desired byte accesses.
13 6.42
IDT707288S/L High-Speed 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1)
707288X15 Com'l Only Symbol INTERRUPT TIMING tAS tWR tINS tINR Address Set-up Time Write Recovery Time Interrupt Set Time Interrupt Reset Time 0 0
____ ____ ____ ____
707288X20 Com'l & Ind Min. Max.
707288X25 Com'l & Ind Min. Max. Unit
Parameter
Min.
Max.
0 0
____ ____
____ ____
0 0
____ ____
____ ____
ns ns ns ns
3592 tbl 16
15 15
20 20
25 25
NOTES: 1. 'X' in part numbers indicates power rating (S or L).
Waveform of Interrupt Timing(1,5)
tWC ADDR"A" tAS MBSEL"A"
(3)
MAILBOX SET ADDRESS
(2) (4)
tWR
R/W"A" tINS INT"B"
3592 drw 12 (3)
tRC ADDR"B" tAS MBSEL"B"
(3)
MAILBOX CLEAR ADDRESS
(2)
OE"B" tINR INT"B"
3592 drw 13 (3)
NOTES: 1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A". 2. See Interrupt Truth Table V. 3. Timing depends on which enable signal (CE or R/W) is asserted last. 4. Timing depends on which enable signal (CE or R/W) is de-asserted first. 5. Refer to Truth Table I.
6.42 14
IDT707288S/L High-Speed 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Depth and Width Expansion
The IDT707288 features dual chip enables (refer to Truth Table I) in order to facilitate rapid and simple depth expansion with no requirements for external logic. Figure 4 illustrates how to control the various chip enables in order to expand two devices in depth. The IDT707288 can also be used in applications requiring expanded width, as indicated in Figure 4. Since the banks are allocated at the discretion of the user, the external controller can be set up to drive the input signals for the various devices as required to allow for 32-bit or wider applications.
A14(1)
IDT707288 Bank-Switchable SRAM
CE0 CE1 VCC
IDT707288 Bank-Switchable SRAM
CE0 CE1 VCC
Control Inputs
Control Inputs
IDT707288 Bank-Switchable SRAM
CE1 CE0
IDT707288 Bank-Switchable SRAM
CE1 CE0 BKSEL0-3 R/W LB, UB OE
Control Inputs
Control Inputs
3592 drw 14
Figure 4. Depth and Width Expansion with IDT707288 NOTE: 1. This signal is provided by external logic. It is not a bit present on the address bus.
15 6.42
IDT707288S/L High-Speed 64K x 16 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
IDT XXXXX Device Type A Power 999 Speed A Package A Process/ Temperature Range Blank I Commercial (0C to +70C) Industrial (-40C to +85C)
PF
100-pin TQFP (PN100-1)
15 20 25
Commercial Only Commercial & Industrial Commercial & Industrial
Speed in nanoseconds
.
S L 707288
Standard Power Low Power 1Mbit (4 x 16K x 16) Bank-Switchable Dual-Ported SRAM with External Bank Selects
3592 drw 15
Datasheet Document History
1/18/99: Initiated datasheet document history Converted to new format Cosmetic and typographical corrections Page 2 Added additional notes to pin configurations Removed preliminary note Cosmetic and typographical corrections Changed drawing format Page 1 Corrected DSC number Added Industrial Temperature Ranges and removed corresponding notes Replaced IDT logo Page 1 Made overbar correction on drawing Changed 200mV to 0mV in notes Page 5 Increased storage temperature parameter Clarified TA parameter Page 6 DC Electrical parameters-changed wording from "open" to "disabled"
3/11/99: 6/4/99: 3/10/00:
5/23/00:
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: 831-754-4613 DualPortHelp@idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42 16

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